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爾灣(橘郡),加州
Here are our current openings for
our Irvine office. Please follow the links
for detailed description.
Position: Senior Mixed-Signal Design
Engineer
Number of Positions: 2
Category: Engineering
Position Type: Full-time
Travel Requirement: <10%
Description:
This role involves design and execution
of circuits related to CMOS Image Sensor,
such as ADC, DAC, Programmable Gain Amplifier,
etc. The candidate will work closely with
a team that has expertise in device physics,
analog / digital circuit design, and image
processing. This position requires close
interaction with foundry, testing, packaging,
and system house. Work with marketing /
application engineers to translate product
specifications in to circuit requirements
and perform tradeoff analysis. Participate
in system level architectural design of
sensors and SOC.
The company will consider the right candidate
with less experience (2-5years) for one
of the two positions.
Requirements:
• BS EE required; MS EE or equivalent
is preferred
• 5 years minimum experience in CMOS
mixed-signal / analog circuit design
• Proficient in CAD tools such as
HSPICE, HSIM, Cadence
• Experience in low-noise switch-capacitor
circuit design necessary
• Experience in layout is required
• Proven track record of taking design
to mass production is necessary, including
chip debugging and yield improvement
• Knowledge of ADC, PLL, DAC, Voltage
Reference design is stressed
• System-level knowledge is a plus
• Experience in CMOS Image Sensor
area / semiconductor device physics / optics
knowledge is a plus
• Team player with good communication and presentation
skills
Position: Senior ASIC Design Engineer
Number of Positions: 1
Category: Engineering
Position Type: Full-Time
Travel Requirement: <10 %
Description:
This role involves working closely with
experienced design and system engineering
teams using state of the art technologies
to develop CMOS image sensors and SOC solutions
for mobile consumer electronics and smart
sensor markets. The Sr. ASIC Engineer will
be a key contributor to the design and integration
of digital image signal processing (ISP)
blocks; from initial specification and algorithm
development through hardware implementation,
tapeout, device validation and test support.
The ideal candidate should possess strong
VLSI design experience including RTL/logic
design, behavioral and gate level simulations,
timing and power analysis and closure, gate
count optimization, and tradeoff analysis.
Requirements:
• BS EE required degree with 8 years
of experience, or MSEE with 6 years of experience
• Strong Verilog HDL programming skill
required
• Solid experience in simulation modeling,
block and chip level verification, and RTL
synthesis
• Experience working with FPGA platforms,
for prototyping designs, silicon bring up
and validation
• Hands on lab experience with a variety
of test equipments including oscilloscopes
and logic analyzers
• TCL, and C/C++ programming skills
preferred; System Verilog or assertion based
verification background a plus
• Knowledge of ISP algorithm, concepts
of CMOS image sensor, and understanding
of analog/digital interfaces and techniques
is a definitely a plus
• Well organized, methodical, and
detail oriented.
• Team player with good communication and presentation
skills
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